Dramatic advances have been made in miniaturizing and packaging electronic devices in the time since the first computers were developed. One need only compare the room-sized computers of the early 1950's with today's laptop and notebook computers to appreciate just how dramatic these advances have been. Today's notebook computers are modestly priced, can be less than one inch thick, have a footprint no larger than an 8 1/2" by 11" piece of paper, operate for hours off of battery power, contain many megabytes of memory, hundreds of megabytes of magnetic storage (hard disk), and execute tens of millions of instructions per second. By way of contrast, the earliest computers cost millions of dollars, could typically fill an entire room, required massive amounts of power and cooling, had very little memory and storage capability, and could execute only about one thousand instructions per second.
This miniaturization and performance increase is due, in large part, to dramatic advances in semiconductor technology, particularly in semiconductor processing and packaging. A single modern semiconductor integrated circuit die no more than one half inch square can contain millions of transistors. Combined with high-density packaging techniques, modern semiconductor device assemblies provide almost unbelievable amounts of function in an almost unbelievably small package. Notwithstanding these tremendous advances in semiconductor processing and assembly techniques, there is still a great demand for even further improvement in package density.
Modern semiconductor device assemblies are typified by a semiconductor die mounted within a die-receiving cavity of a protective package (or on a leadframe, or other substrate). I/O (Input/Output) pads on the die are electrically connected, within the body of the package, to conductive traces or leads which extend to the exterior of the package, where they terminate in conductive leads, pins, pads, balls or fingers to which further electrical connections are made. Typically the package is mounted to a circuit board having a number of other electronic devices mounted thereto, some of which may be other semiconductor device assemblies. The packages serve to dissipate heat from the die, to protect it from moisture, and to provide a durable exterior which protects the die from physical damage.
As semiconductor device geometries (e.g., line width) become smaller, it becomes possible to provide ever greater numbers of transistors on a semiconductor die. Several limitations come about as a result of conventional packaging techniques, however. For example, very large integrated circuits (i.e., containing large numbers of transistors or other integrated electronic components) tend to require large numbers of I/O connection points (many hundreds in some cases). Although these connection points can be placed very densely on a semiconductor die, there are physical limits to how closely they can be spaced on the exterior of a package body. It is not uncommon, due to a large number of connections, that a one half inch square die must be mounted in a 2 to 3 inch square package body in order to provide sufficient space on the package body for the relatively large and coarsely spaced I/O pins.
Further, a large package body can negate many of the speed benefits which result from small device geometries. Large packages adversely affect how closely semiconductor devices can be spaced on a circuit board or substrate. This, in turn, tends to lengthen the conductive paths (wiring) between the semiconductor devices (i.e., the wiring distance between interconnected I/O pads of two integrated circuit dies). In modern high-speed electronic assemblies, wiring delays can have a significant effect on overall performance. As a result, it is often necessary to find ways to package semiconductor devices so that interconnection length (wiring length) is minimized. (Other factors, such as market-driven demands for ever-smaller consumer products, are not insignificant considerations in applying pressure on semiconductor producers to find ways to package semiconductor devices densely. )
"Chip-on-board" and "flip-chip" manufacturing techniques are high-density electronic device assembly techniques which have been developed in response to pressure for high-density electronic packaging techniques. In both of these techniques, one or more un-packaged (essentially bare) semiconductor dies are mounted directly to tiny "printed circuit boards" and wire to one another in close proximity. In chip-on-board assemblies, a semiconductor die is usually "glued" by its back surface to a circuit-board substrate. Electrical connections are then formed to the die with tiny bond wires, similar to the connections formed to a die within the die-receiving area of a conventional package. Unlike the conventional package, however, there is no intermediate package body between the die and the substrate (circuit board). This permits the die to be place very closely to other electronic devices (including other dies) and for interconnection length to be minimized. After mounting and connection, a protective layer (e.g., an epoxy glob or other suitable protective covering) is disposed over the die and its exposed connections (e.g., the bond wires).
"Flip-chip" manufacturing techniques are similar in some respects (efficient use of area) to chip-on-board techniques, but in flip-chip assemblies, the substrate itself can be another die. Flip-chip techniques involve soldering one or more semiconductor (silicon) chips (one is discussed), in face-to-face relationship, to a substrate (or to another die). Typically, solder balls (otherwise known as pads or bumps) are formed (raised above the planar surface of the chip and substrate) on facing surfaces of both the chip and the substrate at intended points of contact between the two, liquid flux (rosin) is often applied to the face of the chip and/or substrate, the chip is mechanically held in register with the substrate, and the chip and the substrate are subjected to elevated temperature to effect soldering, or fusion of the solder balls on the chip and the corresponding solder balls on the substrate.
The "solder balls" on either the chip or substrate, typically those on the substrate, may be solderable metallized surfaces. The soldering process may be carried out in a reducing atmosphere. A typical flip-chip structure is shown in FIG. 1, and is discussed in greater detail hereinafter.
Previous systems of rigid attachment of chips to chucks have been used for chip alignment, but they must allow some degree of compliance because the chips tend to change relative alignment during soldering by surface tension between the solder balls. The addition of liquid flux to the chip/substrate (flip-chip) assembly creates capillary attraction between the chip and the substrate, which serves to mis-align the chip with respect to the substrate. This is illustrated in FIG. 2, and is discussed in greater detail hereinafter. Further, much of the flux that is applied to the flip-chip assembly is wasted. Still further, the dimension of the remaining gap between the chip and the substrate and the mechanical properties of the solder joints formed by the solder balls and corresponding solder balls tends to be indeterminate.
As discussed hereinabove, direct assembly of semiconductor dies into flip-chip type assemblies can be difficult. When successful, however, such assemblies can provide extremely dense electronic assemblies. In some cases, this high density can create another problem: heat build-up. Whereas in "traditional" packaging techniques the package body and spacing between packages provides for a certain amount of natural, inherent heat dissipation, flip-chip assemblies place chips in very close proximity. This can cause localized "hot-spots" within the flip-chip assembly, particularly where very high switching speeds are involved.
Other problems derive from the close spacing of dies in flip-chip assemblies. With circuits and systems built from "traditionally" packaged electronic devices, there is usually sufficient board space available that providing termination networks for high-speed signals and busses does not require significant additional space (as a portion of the total space required for the circuit or system). With flip-chip assemblies, however, since the total amount of space is so small, any additional space required for termination networks (or other discrete active or passive electronic circuitry) can represent a significant increase in total space.
Accordingly, the present invention is directed to solving these and other related problems (e.g.: alignment during assembly of flip-chip devices; application, control, and removal of solder flux; heat dissipation within dense semiconductor assemblies; space required by termination networks; etc.). Since many of these problems apply to a relatively broad class of dense semiconductor assemblies, the present invention is more broadly (i.e., than chip-to-chip) directed to connecting one or more semiconductor "chips" (dies) to one or more "substrates" such as other semiconductor dies, printed circuit (or wiring) boards, and the like. The resulting assembly is termed a "flip-chip structure" for the purposes of the present invention.